Low Resource FPGA Based Time-to-Digital Converter

Abstract

For the precise measurement of the time difference between the arrival of different signals coming from the different channels, the time-to-digital converter (TDC) implemented in Field Programmable Gate Array (FPGA) is a very useful device. The TDC implemented so far are  basically tapped delay lines which provides a resolution of about 10 ps however such high resolution is necessary for some specific applications. So a low resource TDC implemented in FPGA is preferred which helps to measure the time difference between the signals.

Keywords: analog-to-digital converter (ADC), resolution, DPLL, clock generation, jitter